Merge requests · 敏捷攀樹協會 / 社群 / Digital Logic Design · GitLab

Resolve "20230302 課程內容"

!62 · created Mar 02, 2023 by 晨知吳
Done
updated Sep 01, 2023
Resolve "full adder markdown"

!48 · created Nov 24, 2022 by 晨知吳 kung sheng-jun具備基礎verilog能力
Digital Design Verilog Verilog硬體描述語言實務第二版 enhancement
updated Sep 01, 2023
Resolve "Full adder 電路圖"

!34 · created Nov 10, 2022 by 晨知吳洪偉哲具備verilog能力
Digital Design Verilog Verilog硬體描述語言實務第二版 enhancement
- Merged
- 5
updated Sep 01, 2023
Resolve "Snake"

!53 · created Dec 06, 2022 by 晨知吳 FPGA系統設計實務
Digital Design Doing Verilog Verilog硬體描述語言實務第二版 documentation enhancement
- Merged
- 1
updated Sep 01, 2023
Resolve "AND OR XOR XNOR NAND NOR NOT BUF"

!46 · created Nov 24, 2022 by 晨知吳潘中義具備 Verilog的能力
VHDL數位邏輯設計入門實務 Verilog
- Merged
- Approved
updated Sep 01, 2023
Resolve "shift microoperation"

!61 · created Mar 02, 2023 by 晨知吳 CPU
Assembly Language Computer System Architecture Doing Verilog enhancement
updated Sep 01, 2023
Resolve "4-bit full adder markdown"

!44 · created Nov 23, 2022 by 晨知吳 Verilog硬體描述語言實務第二版 tempbranch
Digital Design Done Reference Verilog Verilog硬體描述語言實務第二版
- Merged
- Approved
updated Mar 11, 2023
Resolve "最大值max 中間值mid 最小值min 模擬圖"

!55 · created Dec 08, 2022 by 晨知吳林聖翔具備基礎verilog能力
Digital Design To Do Verilog Verilog硬體描述語言實務第二版
- Merged
- 1
- Approved
updated Mar 11, 2023
Resolve "data flow verilog"

!51 · created Dec 05, 2022 by 晨知吳
Digital Design Verilog Verilog硬體描述語言實務第二版
- Merged
- 4
- Approved
updated Mar 02, 2023
Resolve "4bit adder verilog and test by高"

!45 · created Nov 23, 2022 by 晨知吳高輝翔具備基礎verilog能力
Digital Design Verilog Verilog硬體描述語言實務第二版
- Merged
- 5
updated Dec 15, 2022
Resolve "if_else verilog"

!56 · created Dec 10, 2022 by 晨知吳吳琝貴具備基礎verilog能力
Digital Design Verilog Verilog硬體描述語言實務第二版
- Merged
updated Dec 15, 2022
Resolve "Data Flow 模擬圖"

!54 · created Dec 07, 2022 by 晨知吳林聖翔具備基礎verilog能力
Digital Design Doing Verilog Verilog硬體描述語言實務第二版
- Merged
- Approved
updated Dec 15, 2022
Resolve "4-bit full adder電路圖"

!49 · created Dec 01, 2022 by 晨知吳洪偉哲具備verilog能力
Digital Design To Do Verilog Verilog硬體描述語言實務第二版
- Merged
- Approved
updated Dec 15, 2022
Resolve "full adder Verilog"

!35 · created Nov 10, 2022 by 晨知吳吳琝貴具備基礎verilog能力
Digital Design Verilog Verilog硬體描述語言實務第二版
- Merged
- 5
- Approved
updated Dec 15, 2022
Resolve "full adder verilog_test"

!36 · created Nov 10, 2022 by 晨知吳高輝翔具備基礎verilog能力
Digital Design Verilog Verilog硬體描述語言實務第二版
- Merged
- 3
- Approved
updated Dec 15, 2022
Resolve "logic microoperation"

!41 · created Nov 19, 2022 by 晨知吳 CPU
Assembly Language Computer System Architecture Verilog 計算機系統結構
updated Dec 15, 2022
Resolve "4bit adder verilog and test"

!42 · created Nov 23, 2022 by 晨知吳吳琝貴具備基礎verilog能力
Digital Design To Do Verilog Verilog硬體描述語言實務第二版
- Merged
- 1
- Approved
updated Dec 15, 2022
Resolve "4位元加法器模擬圖"

!43 · created Nov 23, 2022 by 晨知吳林聖翔具備基礎verilog能力
Digital Design To Do Verilog Verilog硬體描述語言實務第二版
updated Dec 15, 2022
Resolve "if_else 電路圖"

!57 · created Dec 12, 2022 by 晨知吳
Digital Design Verilog Verilog硬體描述語言實務第二版
- Merged
- 7
updated Dec 15, 2022
Resolve "FPGA可程式邏輯閘陣列介紹"

!14 · created Sep 12, 2022 by 晨知吳著作
Digital Design Digital Systm Design Logic Design Verilog 硬體描述語言程式設計與模擬
- Merged
- 1
updated Dec 06, 2022

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