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Updated date
Relate #61 !53 提交將更新縮排
!63
· created
Sep 01, 2023
by
晨知 吳
FPGA系統設計實務
Digital Design
To Do
Verilog
Verilog硬體描述語言實務 第二版
documentation
enhancement
Closed
updated
Sep 01, 2023
Draft: Resolve "亂數產生器"
!60
· created
Jan 01, 2023
by
晨知 吳
FPGA系統設計實務
Digital Design
Doing
Verilog
documentation
enhancement
Closed
updated
Jan 01, 2023
Relate# 作業
!25
· created
Nov 03, 2022
by
晨知 吳
洪偉哲具備verilog能力
Digital Design
Verilog
Verilog硬體描述語言實務 第二版
Closed
updated
Dec 06, 2022
Draft: Resolve "full add"
!33
· created
Nov 10, 2022
by
晨知 吳
Verilog硬體描述語言實務 第二版
Digital Design
Verilog硬體描述語言實務 第二版
Closed
updated
Dec 06, 2022
Draft: Resolve "AND OR XOR XNOR NAND NOR NOT BUF"
!19
· created
Oct 28, 2022
by
晨知 吳
洪偉哲具備verilog能力
Digital Design
Verilog
Verilog硬體描述語言實務 第二版
Closed
updated
Nov 20, 2022
Draft: Resolve "AND OR XOR XNOR NAND NOR NOT BUF"
!17
· created
Oct 27, 2022
by
晨知 吳
林聖翔具備基礎verilog能力
Digital Design
Verilog
Verilog硬體描述語言實務 第二版
Closed
updated
Nov 20, 2022
Draft: Resolve "AND OR XOR XNOR NAND NOR NOT BUF"
!15
· created
Oct 27, 2022
by
晨知 吳
課程規劃與設計
Digital Design
Verilog
Verilog硬體描述語言實務 第二版
Closed
updated
Nov 20, 2022
Draft: Resolve "AND OR XOR XNOR NAND NOR NOT BUF"
!18
· created
Oct 27, 2022
by
晨知 吳
吳琝貴具備基礎verilog能力
Digital Design
Verilog
Verilog硬體描述語言實務 第二版
Closed
updated
Nov 20, 2022
Draft: Resolve "AND OR XOR XNOR NAND NOR NOT BUF"
1 of 8 checklist items completed
!24
· created
Nov 03, 2022
by
晨知 吳
kung sheng-jun具備基礎verilog能力
Logic Design
Verilog
Verilog硬體描述語言實務 第二版
Closed
1
updated
Nov 20, 2022
Draft: Resolve "AND OR XOR XNOR NAND NOR NOT BUF"
!23
· created
Nov 03, 2022
by
晨知 吳
高輝翔具備基礎verilog能力
Digital Design
Verilog
Verilog硬體描述語言實務 第二版
Closed
updated
Nov 20, 2022
Resolve "AND OR XOR NAND NOT BUF NOR"
!29
· created
Nov 10, 2022
by
晨知 吳
Verilog硬體描述語言實務 第二版
Digital Design
Reference
Verilog
Verilog硬體描述語言實務 第二版
Closed
updated
Nov 20, 2022
Draft: Resolve "full adder 模擬圖"
!40
· created
Nov 17, 2022
by
晨知 吳
林聖翔具備基礎verilog能力
Digital Design
Done
Verilog
Verilog硬體描述語言實務 第二版
Closed
updated
Nov 17, 2022
Draft: Resolve "full adder markdown"
!39
· created
Nov 17, 2022
by
晨知 吳
kung sheng-jun具備基礎verilog能力
Digital Design
Verilog
Verilog硬體描述語言實務 第二版
enhancement
Closed
updated
Nov 17, 2022
Draft: Resolve "霹靂燈 Perak Light"
!27
· created
Nov 07, 2022
by
晨知 吳
FPGA系統設計實務
Digital Design
To Do
Verilog
enhancement
Closed
updated
Nov 07, 2022
Draft: Resolve "霹靂燈"
!26
· created
Nov 07, 2022
by
晨知 吳
FPGA系統設計實務
Digital Design
To Do
Verilog
enhancement
Closed
updated
Nov 07, 2022
Draft: Resolve "上下數計數器"
!22
· created
Nov 03, 2022
by
晨知 吳
FPGA系統設計實務
Digital Communications
Verilog
Verilog硬體描述語言實務 第二版
enhancement
Closed
updated
Nov 07, 2022
Draft: Resolve "AND OR XOR XNOR NAND NOR NOT BUF"
!16
· created
Oct 27, 2022
by
晨知 吳
林軒霆具備基礎verilog能力
Digital Design
Verilog
Verilog硬體描述語言實務 第二版
Closed
updated
Nov 02, 2022
Draft: Resolve "Book Digital Design 第七章 組合邏輯電路設計"
!4
· created
Sep 22, 2021
by
晨知 吳
著作
Book
Digital Design
documentation
Closed
updated
Sep 22, 2021