潘中義具備 Verilog的能力 · Milestones · 敏捷攀樹協會 / 社群 / Digital Logic Design · GitLab

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Milestone Nov 24, 2022–Jan 14, 2023

潘中義具備 Verilog的能力

Issues 1
Merge requests 1
Participants 1
Labels 3

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Start date

Nov 24, 2022

Nov 24 2022

-

Jan 14 2023

Due date

Jan 14, 2023 (Past due)

1

Issues 1 New issue

Open: 0 Closed: 1

1

Merge requests 1

Open: 0 Closed: 0 Merged: 1

0

Releases

None

Reference: atca/community-edition/digital-logic-design%"潘中義具備 Verilog的能力"