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Closed
Milestone
Sep 5, 2022–Jan 8, 2023
洪偉哲具備verilog能力
具備verizon獨立撰寫程式能力,可依照需求撰寫電路功能
會看模擬結果並修正程式錯誤與問題
會燒錄到FPGA,並以邏輯分析儀或實際動作修正結果
Issues
4
Merge requests
4
Participants
1
Labels
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