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Closed
Milestone
Sep 5, 2022–Jan 8, 2023
高輝翔具備基礎verilog能力
具備Verilog獨立撰寫程式能力,可依照需求撰寫電路功能
會看模擬結果並修正程式錯誤
會燒錄到FPGA,以實際結果看到修正問題
Issues
4
Merge requests
3
Participants
1
Labels
5
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