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Sep 5, 2022–Jan 15, 2023
kung sheng-jun具備基礎verilog能力
具備Verilog獨立填寫程式能力, 可依照需求填寫電路問題
會看模擬並修正問題
會燒錄到FPGA,以實際結果看到修正問題
Issues
4
Merge requests
6
Participants
1
Labels
6
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