Merge requests · 敏捷攀樹協會 / 社群 / Digital Logic Design · GitLab

Resolve "4-bit full adder markdown"

!44 · created Nov 23, 2022 by 晨知吳 Verilog硬體描述語言實務第二版 tempbranch
Digital Design Done Reference Verilog Verilog硬體描述語言實務第二版
- Merged
- Approved
updated Mar 11, 2023
Resolve "4位元加法器模擬圖"

!43 · created Nov 23, 2022 by 晨知吳林聖翔具備基礎verilog能力
Digital Design To Do Verilog Verilog硬體描述語言實務第二版
updated Dec 15, 2022
Resolve "4bit adder verilog and test"

!42 · created Nov 23, 2022 by 晨知吳吳琝貴具備基礎verilog能力
Digital Design To Do Verilog Verilog硬體描述語言實務第二版
- Merged
- 1
- Approved
updated Dec 15, 2022
Resolve "logic microoperation"

!41 · created Nov 19, 2022 by 晨知吳 CPU
Assembly Language Computer System Architecture Verilog 計算機系統結構
updated Dec 15, 2022
Draft: Resolve "full adder 模擬圖"

!40 · created Nov 17, 2022 by 晨知吳林聖翔具備基礎verilog能力
Digital Design Done Verilog Verilog硬體描述語言實務第二版
- Closed
updated Nov 17, 2022
Draft: Resolve "full adder markdown"

!39 · created Nov 17, 2022 by 晨知吳 kung sheng-jun具備基礎verilog能力
Digital Design Verilog Verilog硬體描述語言實務第二版 enhancement
- Closed
updated Nov 17, 2022
Resolve "full adder 真值表"

!38 · created Nov 17, 2022 by 晨知吳蘇冠雄具備基礎verilog的能力
Digital Design Verilog Verilog硬體描述語言實務第二版 enhancement
- Merged
- 2
- Approved
updated Nov 24, 2022
Resolve "topic arithmetic microoperation"

!37 · created Nov 14, 2022 by 晨知吳 CPU
Assembly Language Computer System Architecture Doing Verilog enhancement
- Merged
- Approved
updated Nov 20, 2022
Resolve "full adder verilog_test"

!36 · created Nov 10, 2022 by 晨知吳高輝翔具備基礎verilog能力
Digital Design Verilog Verilog硬體描述語言實務第二版
- Merged
- 3
- Approved
updated Dec 15, 2022
Resolve "full adder Verilog"

!35 · created Nov 10, 2022 by 晨知吳吳琝貴具備基礎verilog能力
Digital Design Verilog Verilog硬體描述語言實務第二版
- Merged
- 5
- Approved
updated Dec 15, 2022
Resolve "Full adder 電路圖"

!34 · created Nov 10, 2022 by 晨知吳洪偉哲具備verilog能力
Digital Design Verilog Verilog硬體描述語言實務第二版 enhancement
- Merged
- 5
updated Sep 01, 2023
Draft: Resolve "full add"

!33 · created Nov 10, 2022 by 晨知吳 Verilog硬體描述語言實務第二版
Digital Design Verilog硬體描述語言實務第二版
- Closed
updated Dec 06, 2022
Resolve "full adder markdown"

!32 · created Nov 10, 2022 by 晨知吳 kung sheng-jun具備基礎verilog能力 tempbranch
Digital Design Done Verilog Verilog硬體描述語言實務第二版 enhancement
updated Nov 24, 2022
Resolve "full adder 模擬圖"

!31 · created Nov 10, 2022 by 晨知吳林聖翔具備基礎verilog能力
Digital Design Verilog Verilog硬體描述語言實務第二版
- Merged
- 6
updated Nov 24, 2022
Resolve "full adder code review"

!30 · created Nov 10, 2022 by 晨知吳林軒霆具備基礎verilog能力
Digital Design Verilog Verilog硬體描述語言實務第二版 enhancement
- 1
- Approved
updated Sep 01, 2023
Resolve "AND OR XOR NAND NOT BUF NOR"

!29 · created Nov 10, 2022 by 晨知吳 Verilog硬體描述語言實務第二版
Digital Design Reference Verilog Verilog硬體描述語言實務第二版
- Closed
updated Nov 20, 2022
Resolve "霹靂燈 Perak Light"

!28 · created Nov 07, 2022 by 晨知吳 FPGA系統設計實務
Digital Design To Do Verilog enhancement
- Merged
- 2
updated Dec 06, 2022
Draft: Resolve "霹靂燈 Perak Light"

!27 · created Nov 07, 2022 by 晨知吳 FPGA系統設計實務
Digital Design To Do Verilog enhancement
- Closed
updated Nov 07, 2022
Draft: Resolve "霹靂燈"

!26 · created Nov 07, 2022 by 晨知吳 FPGA系統設計實務
Digital Design To Do Verilog enhancement
- Closed
updated Nov 07, 2022
Relate# 作業

!25 · created Nov 03, 2022 by 晨知吳洪偉哲具備verilog能力
Digital Design Verilog Verilog硬體描述語言實務第二版
- Closed
updated Dec 06, 2022

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