Merge requests · 敏捷攀樹協會 / 社群 / Digital Logic Design · GitLab

Resolve "最大值max 中間值mid 最小值min 模擬圖"

!55 · created Dec 08, 2022 by 晨知吳林聖翔具備基礎verilog能力
Digital Design To Do Verilog Verilog硬體描述語言實務第二版
- Merged
- 1
- Approved
updated Mar 11, 2023
Resolve "Data Flow 模擬圖"

!54 · created Dec 07, 2022 by 晨知吳林聖翔具備基礎verilog能力
Digital Design Doing Verilog Verilog硬體描述語言實務第二版
- Merged
- Approved
updated Dec 15, 2022
Draft: Resolve "full adder 模擬圖"

!47 · created Nov 24, 2022 by 晨知吳林聖翔具備基礎verilog能力
Digital Design To Do Verilog Verilog硬體描述語言實務第二版
updated Nov 24, 2022
Resolve "4位元加法器模擬圖"

!43 · created Nov 23, 2022 by 晨知吳林聖翔具備基礎verilog能力
Digital Design To Do Verilog Verilog硬體描述語言實務第二版
updated Dec 15, 2022
Draft: Resolve "full adder 模擬圖"

!40 · created Nov 17, 2022 by 晨知吳林聖翔具備基礎verilog能力
Digital Design Done Verilog Verilog硬體描述語言實務第二版
- Closed
updated Nov 17, 2022
Resolve "full adder 模擬圖"

!31 · created Nov 10, 2022 by 晨知吳林聖翔具備基礎verilog能力
Digital Design Verilog Verilog硬體描述語言實務第二版
- Merged
- 6
updated Nov 24, 2022
Draft: Resolve "AND OR XOR XNOR NAND NOR NOT BUF"

!17 · created Oct 27, 2022 by 晨知吳林聖翔具備基礎verilog能力
Digital Design Verilog Verilog硬體描述語言實務第二版
- Closed
updated Nov 20, 2022