Merge requests · 敏捷攀樹協會 / 社群 / Digital Logic Design · GitLab

Resolve "if_else verilog"

!56 · created Dec 10, 2022 by 晨知吳吳琝貴具備基礎verilog能力
Digital Design Verilog Verilog硬體描述語言實務第二版
- Merged
updated Dec 15, 2022
Resolve "4bit adder verilog and test"

!42 · created Nov 23, 2022 by 晨知吳吳琝貴具備基礎verilog能力
Digital Design To Do Verilog Verilog硬體描述語言實務第二版
- Merged
- 1
- Approved
updated Dec 15, 2022
Resolve "full adder Verilog"

!35 · created Nov 10, 2022 by 晨知吳吳琝貴具備基礎verilog能力
Digital Design Verilog Verilog硬體描述語言實務第二版
- Merged
- 5
- Approved
updated Dec 15, 2022
Draft: Resolve "AND OR XOR XNOR NAND NOR NOT BUF"

!18 · created Oct 27, 2022 by 晨知吳吳琝貴具備基礎verilog能力
Digital Design Verilog Verilog硬體描述語言實務第二版
- Closed
updated Nov 20, 2022