Merge requests · 敏捷攀樹協會 / 社群 / Digital Logic Design · GitLab

Relate #61 !53 提交將更新縮排

!63 · created Sep 01, 2023 by 晨知吳 FPGA系統設計實務
Digital Design To Do Verilog Verilog硬體描述語言實務第二版 documentation enhancement
- Closed
updated Sep 01, 2023
Draft: Resolve "亂數產生器"

!60 · created Jan 01, 2023 by 晨知吳 FPGA系統設計實務
Digital Design Doing Verilog documentation enhancement
- Closed
updated Jan 01, 2023
Draft: Resolve "full adder markdown"

!39 · created Nov 17, 2022 by 晨知吳 kung sheng-jun具備基礎verilog能力
Digital Design Verilog Verilog硬體描述語言實務第二版 enhancement
- Closed
updated Nov 17, 2022
Draft: Resolve "霹靂燈 Perak Light"

!27 · created Nov 07, 2022 by 晨知吳 FPGA系統設計實務
Digital Design To Do Verilog enhancement
- Closed
updated Nov 07, 2022
Draft: Resolve "霹靂燈"

!26 · created Nov 07, 2022 by 晨知吳 FPGA系統設計實務
Digital Design To Do Verilog enhancement
- Closed
updated Nov 07, 2022
Draft: Resolve "上下數計數器"

!22 · created Nov 03, 2022 by 晨知吳 FPGA系統設計實務
Digital Communications Verilog Verilog硬體描述語言實務第二版 enhancement
- Closed
updated Nov 07, 2022