Merge requests · 敏捷攀樹協會 / 社群 / Digital Logic Design · GitLab

Relate #61 !53 提交將更新縮排

!63 · created Sep 01, 2023 by 晨知吳 FPGA系統設計實務
Digital Design To Do Verilog Verilog硬體描述語言實務第二版 documentation enhancement
- Closed
updated Sep 01, 2023
Resolve "shift microoperation"

!61 · created Mar 02, 2023 by 晨知吳 CPU
Assembly Language Computer System Architecture Doing Verilog enhancement
updated Sep 01, 2023
Draft: Resolve "亂數產生器"

!60 · created Jan 01, 2023 by 晨知吳 FPGA系統設計實務
Digital Design Doing Verilog documentation enhancement
- Closed
updated Jan 01, 2023
Resolve "Snake"

!53 · created Dec 06, 2022 by 晨知吳 FPGA系統設計實務
Digital Design Doing Verilog Verilog硬體描述語言實務第二版 documentation enhancement
- Merged
- 1
updated Sep 01, 2023
Resolve "full adder markdown"

!48 · created Nov 24, 2022 by 晨知吳 kung sheng-jun具備基礎verilog能力
Digital Design Verilog Verilog硬體描述語言實務第二版 enhancement
updated Sep 01, 2023
Draft: Resolve "full adder markdown"

!39 · created Nov 17, 2022 by 晨知吳 kung sheng-jun具備基礎verilog能力
Digital Design Verilog Verilog硬體描述語言實務第二版 enhancement
- Closed
updated Nov 17, 2022
Resolve "full adder 真值表"

!38 · created Nov 17, 2022 by 晨知吳蘇冠雄具備基礎verilog的能力
Digital Design Verilog Verilog硬體描述語言實務第二版 enhancement
- Merged
- 2
- Approved
updated Nov 24, 2022
Resolve "topic arithmetic microoperation"

!37 · created Nov 14, 2022 by 晨知吳 CPU
Assembly Language Computer System Architecture Doing Verilog enhancement
- Merged
- Approved
updated Nov 20, 2022
Resolve "Full adder 電路圖"

!34 · created Nov 10, 2022 by 晨知吳洪偉哲具備verilog能力
Digital Design Verilog Verilog硬體描述語言實務第二版 enhancement
- Merged
- 5
updated Sep 01, 2023
Resolve "full adder markdown"

!32 · created Nov 10, 2022 by 晨知吳 kung sheng-jun具備基礎verilog能力 tempbranch
Digital Design Done Verilog Verilog硬體描述語言實務第二版 enhancement
updated Nov 24, 2022
Resolve "full adder code review"

!30 · created Nov 10, 2022 by 晨知吳林軒霆具備基礎verilog能力
Digital Design Verilog Verilog硬體描述語言實務第二版 enhancement
- 1
- Approved
updated Sep 01, 2023
Resolve "霹靂燈 Perak Light"

!28 · created Nov 07, 2022 by 晨知吳 FPGA系統設計實務
Digital Design To Do Verilog enhancement
- Merged
- 2
updated Dec 06, 2022
Draft: Resolve "霹靂燈 Perak Light"

!27 · created Nov 07, 2022 by 晨知吳 FPGA系統設計實務
Digital Design To Do Verilog enhancement
- Closed
updated Nov 07, 2022
Draft: Resolve "霹靂燈"

!26 · created Nov 07, 2022 by 晨知吳 FPGA系統設計實務
Digital Design To Do Verilog enhancement
- Closed
updated Nov 07, 2022
Draft: Resolve "上下數計數器"

!22 · created Nov 03, 2022 by 晨知吳 FPGA系統設計實務
Digital Communications Verilog Verilog硬體描述語言實務第二版 enhancement
- Closed
updated Nov 07, 2022
Resolve "上下數計數器"

!20 · created Oct 31, 2022 by 晨知吳 FPGA系統設計實務
Digital Communications Verilog Verilog硬體描述語言實務第二版 enhancement
updated Nov 14, 2022
Resolve "紅綠燈"

!12 · created Jun 13, 2022 by 晨知吳專題製作
Digital Design To Do documentation enhancement 專題製作
updated Dec 06, 2022