Merge requests · 敏捷攀樹協會 / 社群 / Digital Logic Design · GitLab

Resolve "full adder verilog_test"

!36 · created Nov 10, 2022 by 晨知吳高輝翔具備基礎verilog能力
Digital Design Verilog Verilog硬體描述語言實務第二版
- Merged
- 3
- Approved
updated Dec 15, 2022
Resolve "full adder Verilog"

!35 · created Nov 10, 2022 by 晨知吳吳琝貴具備基礎verilog能力
Digital Design Verilog Verilog硬體描述語言實務第二版
- Merged
- 5
- Approved
updated Dec 15, 2022
Resolve "Full adder 電路圖"

!34 · created Nov 10, 2022 by 晨知吳洪偉哲具備verilog能力
Digital Design Verilog Verilog硬體描述語言實務第二版 enhancement
- Merged
- 5
updated Sep 01, 2023
Draft: Resolve "full add"

!33 · created Nov 10, 2022 by 晨知吳 Verilog硬體描述語言實務第二版
Digital Design Verilog硬體描述語言實務第二版
- Closed
updated Dec 06, 2022
Resolve "full adder markdown"

!32 · created Nov 10, 2022 by 晨知吳 kung sheng-jun具備基礎verilog能力 tempbranch
Digital Design Done Verilog Verilog硬體描述語言實務第二版 enhancement
updated Nov 24, 2022
Resolve "full adder 模擬圖"

!31 · created Nov 10, 2022 by 晨知吳林聖翔具備基礎verilog能力
Digital Design Verilog Verilog硬體描述語言實務第二版
- Merged
- 6
updated Nov 24, 2022
Resolve "full adder code review"

!30 · created Nov 10, 2022 by 晨知吳林軒霆具備基礎verilog能力
Digital Design Verilog Verilog硬體描述語言實務第二版 enhancement
- 1
- Approved
updated Sep 01, 2023
Resolve "AND OR XOR NAND NOT BUF NOR"

!29 · created Nov 10, 2022 by 晨知吳 Verilog硬體描述語言實務第二版
Digital Design Reference Verilog Verilog硬體描述語言實務第二版
- Closed
updated Nov 20, 2022
Relate# 作業

!25 · created Nov 03, 2022 by 晨知吳洪偉哲具備verilog能力
Digital Design Verilog Verilog硬體描述語言實務第二版
- Closed
updated Dec 06, 2022
Draft: Resolve "AND OR XOR XNOR NAND NOR NOT BUF" 1 of 8 checklist items completed

!24 · created Nov 03, 2022 by 晨知吳 kung sheng-jun具備基礎verilog能力
Logic Design Verilog Verilog硬體描述語言實務第二版
- Closed
- 1
updated Nov 20, 2022
Draft: Resolve "AND OR XOR XNOR NAND NOR NOT BUF"

!23 · created Nov 03, 2022 by 晨知吳高輝翔具備基礎verilog能力
Digital Design Verilog Verilog硬體描述語言實務第二版
- Closed
updated Nov 20, 2022
Draft: Resolve "上下數計數器"

!22 · created Nov 03, 2022 by 晨知吳 FPGA系統設計實務
Digital Communications Verilog Verilog硬體描述語言實務第二版 enhancement
- Closed
updated Nov 07, 2022
Resolve "AND OR XOR XNOR NAND NOR NOT BUF"

!21 · created Nov 01, 2022 by 晨知吳林軒霆具備基礎verilog能力
Verilog Verilog硬體描述語言實務第二版
- 1
updated Nov 20, 2022
Resolve "上下數計數器"

!20 · created Oct 31, 2022 by 晨知吳 FPGA系統設計實務
Digital Communications Verilog Verilog硬體描述語言實務第二版 enhancement
updated Nov 14, 2022
Draft: Resolve "AND OR XOR XNOR NAND NOR NOT BUF"

!19 · created Oct 28, 2022 by 晨知吳洪偉哲具備verilog能力
Digital Design Verilog Verilog硬體描述語言實務第二版
- Closed
updated Nov 20, 2022
Draft: Resolve "AND OR XOR XNOR NAND NOR NOT BUF"

!18 · created Oct 27, 2022 by 晨知吳吳琝貴具備基礎verilog能力
Digital Design Verilog Verilog硬體描述語言實務第二版
- Closed
updated Nov 20, 2022
Draft: Resolve "AND OR XOR XNOR NAND NOR NOT BUF"

!17 · created Oct 27, 2022 by 晨知吳林聖翔具備基礎verilog能力
Digital Design Verilog Verilog硬體描述語言實務第二版
- Closed
updated Nov 20, 2022
Draft: Resolve "AND OR XOR XNOR NAND NOR NOT BUF"

!16 · created Oct 27, 2022 by 晨知吳林軒霆具備基礎verilog能力
Digital Design Verilog Verilog硬體描述語言實務第二版
- Closed
updated Nov 02, 2022
Draft: Resolve "AND OR XOR XNOR NAND NOR NOT BUF"

!15 · created Oct 27, 2022 by 晨知吳課程規劃與設計
Digital Design Verilog Verilog硬體描述語言實務第二版
- Closed
updated Nov 20, 2022
Resolve "除頻器"

!11 · created May 24, 2022 by 晨知吳專題製作
Digital Design Doing Reference Verilog硬體描述語言實務第二版硬體描述語言程式設計與模擬
updated Jun 13, 2022

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