Merge requests · 敏捷攀樹協會 / 社群 / Digital Logic Design · GitLab

Relate #61 !53 提交將更新縮排

!63 · created Sep 01, 2023 by 晨知吳 FPGA系統設計實務
Digital Design To Do Verilog Verilog硬體描述語言實務第二版 documentation enhancement
- Closed
updated Sep 01, 2023
Resolve "最大值max 中間值mid 最小值min 模擬圖"

!55 · created Dec 08, 2022 by 晨知吳林聖翔具備基礎verilog能力
Digital Design To Do Verilog Verilog硬體描述語言實務第二版
- Merged
- 1
- Approved
updated Mar 11, 2023
Draft: Resolve "Data Flow Markdown "

!50 · created Dec 01, 2022 by 晨知吳 kung sheng-jun具備基礎verilog能力
Digital Design To Do Verilog Verilog硬體描述語言實務第二版 Vivado
updated Dec 08, 2022
Resolve "4-bit full adder電路圖"

!49 · created Dec 01, 2022 by 晨知吳洪偉哲具備verilog能力
Digital Design To Do Verilog Verilog硬體描述語言實務第二版
- Merged
- Approved
updated Dec 15, 2022
Draft: Resolve "full adder 模擬圖"

!47 · created Nov 24, 2022 by 晨知吳林聖翔具備基礎verilog能力
Digital Design To Do Verilog Verilog硬體描述語言實務第二版
updated Nov 24, 2022
Resolve "4位元加法器模擬圖"

!43 · created Nov 23, 2022 by 晨知吳林聖翔具備基礎verilog能力
Digital Design To Do Verilog Verilog硬體描述語言實務第二版
updated Dec 15, 2022
Resolve "4bit adder verilog and test"

!42 · created Nov 23, 2022 by 晨知吳吳琝貴具備基礎verilog能力
Digital Design To Do Verilog Verilog硬體描述語言實務第二版
- Merged
- 1
- Approved
updated Dec 15, 2022
Resolve "霹靂燈 Perak Light"

!28 · created Nov 07, 2022 by 晨知吳 FPGA系統設計實務
Digital Design To Do Verilog enhancement
- Merged
- 2
updated Dec 06, 2022
Draft: Resolve "霹靂燈 Perak Light"

!27 · created Nov 07, 2022 by 晨知吳 FPGA系統設計實務
Digital Design To Do Verilog enhancement
- Closed
updated Nov 07, 2022
Draft: Resolve "霹靂燈"

!26 · created Nov 07, 2022 by 晨知吳 FPGA系統設計實務
Digital Design To Do Verilog enhancement
- Closed
updated Nov 07, 2022
Resolve "紅綠燈"

!12 · created Jun 13, 2022 by 晨知吳專題製作
Digital Design To Do documentation enhancement 專題製作
updated Dec 06, 2022