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Created date
Resolve "20230302 課程內容"
!62
· created
Mar 02, 2023
by
晨知 吳
Done
Merged
updated
Sep 01, 2023
Resolve "4-bit full adder markdown"
!44
· created
Nov 23, 2022
by
晨知 吳
Verilog硬體描述語言實務 第二版
tempbranch
Digital Design
Done
Reference
Verilog
Verilog硬體描述語言實務 第二版
Merged
Approved
updated
Mar 11, 2023
Draft: Resolve "full adder 模擬圖"
!40
· created
Nov 17, 2022
by
晨知 吳
林聖翔具備基礎verilog能力
Digital Design
Done
Verilog
Verilog硬體描述語言實務 第二版
Closed
updated
Nov 17, 2022
Resolve "full adder markdown"
!32
· created
Nov 10, 2022
by
晨知 吳
kung sheng-jun具備基礎verilog能力
tempbranch
Digital Design
Done
Verilog
Verilog硬體描述語言實務 第二版
enhancement
Merged
updated
Nov 24, 2022
