Merge requests · 敏捷攀樹協會 / 社群 / Digital Logic Design · GitLab

Resolve "Snake"

!53 · created Dec 06, 2022 by 晨知吳 FPGA系統設計實務
Digital Design Doing Verilog Verilog硬體描述語言實務第二版 documentation enhancement
- Merged
- 1
updated Sep 01, 2023
Resolve "shift microoperation"

!61 · created Mar 02, 2023 by 晨知吳 CPU
Assembly Language Computer System Architecture Doing Verilog enhancement
updated Sep 01, 2023
Resolve "Data Flow 模擬圖"

!54 · created Dec 07, 2022 by 晨知吳林聖翔具備基礎verilog能力
Digital Design Doing Verilog Verilog硬體描述語言實務第二版
- Merged
- Approved
updated Dec 15, 2022
Resolve "topic arithmetic microoperation"

!37 · created Nov 14, 2022 by 晨知吳 CPU
Assembly Language Computer System Architecture Doing Verilog enhancement
- Merged
- Approved
updated Nov 20, 2022
Resolve "除頻器"

!11 · created May 24, 2022 by 晨知吳專題製作
Digital Design Doing Reference Verilog硬體描述語言實務第二版硬體描述語言程式設計與模擬
updated Jun 13, 2022
此提交將更新目錄

!10 · created Mar 22, 2022 by 晨知吳著作
Book Digital Design Doing documentation
updated Mar 22, 2022