Merge requests · 敏捷攀樹協會 / 社群 / Digital Logic Design · GitLab

Draft: Resolve "arithmetic logic shift unit"

!64 · created Oct 25, 2023 by 晨知吳著作
ARM CPU Computer System Architecture Digital Design Python
updated Oct 25, 2023
Draft: Resolve "electronic_voting verilog"

!59 · created Dec 28, 2022 by 晨知吳
Doing
- 1
updated Dec 29, 2022
Draft: Resolve "if_else Markdown"

!58 · created Dec 15, 2022 by 晨知吳 kung sheng-jun具備基礎verilog能力
Digital Design Verilog Verilog硬體描述語言實務第二版
Draft: Resolve "Data flow circuit"

!52 · created Dec 06, 2022 by 晨知吳
Digital Design Verilog Verilog硬體描述語言實務第二版
Draft: Resolve "Data Flow Markdown "

!50 · created Dec 01, 2022 by 晨知吳 kung sheng-jun具備基礎verilog能力
Digital Design To Do Verilog Verilog硬體描述語言實務第二版 Vivado
updated Dec 08, 2022
Draft: Resolve "full adder 模擬圖"

!47 · created Nov 24, 2022 by 晨知吳林聖翔具備基礎verilog能力
Digital Design To Do Verilog Verilog硬體描述語言實務第二版
updated Nov 24, 2022
Resolve "full adder code review"

!30 · created Nov 10, 2022 by 晨知吳林軒霆具備基礎verilog能力
Digital Design Verilog Verilog硬體描述語言實務第二版 enhancement
- 1
- Approved
updated Sep 01, 2023
Resolve "AND OR XOR XNOR NAND NOR NOT BUF"

!21 · created Nov 01, 2022 by 晨知吳林軒霆具備基礎verilog能力
Verilog Verilog硬體描述語言實務第二版
- 1
updated Nov 20, 2022
Draft: Resolve "Reference Computer System Architecture Chapter 4"

!9 · created Oct 24, 2021 by 晨知吳計算機系統結構
CPU Computer System Architecture Digital Design Doing Reference 計算機系統結構